Advances in the various components and subsystems utilized for the construction of computer systems have not occurred at an equal pace. For example, the operating frequencies of certain components, such as micro-processors and micro-controllers, have increased at a faster rate than the operating frequencies of other components and system boards. Accordingly, within a single computer system, a number of different components operating at different frequencies is typical.
Other factors which have contributed toward the proliferation of components operating at different frequencies within a computer system include the use of different silicon technologies to manufacture different components, each silicon technology providing a different maximum operating frequency. Further, it is desirable to provide computer systems with the ability to support legacy devices, which may operate at frequencies well below those of more modern components.
A particular device, interface or bus operating at a specific frequency may define a distinct clock domain. The transfer of signals (i.e. data, control or address signals) between various clock domains presents a number of challenges to the designers and manufacturers of computer systems. One solution is to provide an asynchronous data mechanism, in which no synchronization between the clock signals of a transmitting and a receiving time domain is assumed. However, in order to provide a sufficient guarantee that signals are successfully transmitted between time domains, it is typically necessary to provide a fairly elaborate arrangement of latches and control circuitry which increases the data transfer latency between the relevant clock domains. Such circuitry is furthermore power-hungry, and consumes valuable die space.
An alternative solution is to implement synchronous clock domains within a computer system. A synchronous transfer mechanism may be advantageous in that it comprises a relatively uncomplicated circuit structure. A synchronous transfer mechanism may accordingly introduce a reduced transfer latency penalty and may occupy less die space than an asynchronous transfer mechanism.